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BiographyJoel Emer is an Intel Fellow and Director of Microarchitcture Research at Intel in Hudson, Massachusetts and a Professor of the Practice in the Computer Science and Electrical Engineering department at MIT. Previously he worked at Compaq and Digital Equipment Corporation where he held various research and advanced development positions investigating processor microarchitecture for a variety of VAX and Alpha processors and developing performance modeling and evaluation techniques. He has made research contributions in simultaneous multithreading, processor pipeline organization, cache design, memory dependence prediction, performance modeling methodologies, analysis of the architectural impact of soft errors and early contributions to the now pervasive quantitative approach to processor evaluation. His current research interests include memory hierarchy design, processor reliability, reconfigurable logic-based computation and performance modeling.
He received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. He earned a doctorate in electrical engineering from the University of Illinois in 1979. Emer holds over 25 patents and has published more than 35 papers. He is a Fellow of both the ACM and the IEEE, and was the 2009 recipient of the Eckert-Mauchly award for lifetime contributions in computer architecture.
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