Our system for generating ad hoc “cache hierarchies” increases processing speed while reducing energy consumption

For decades computer chips have increased efficiency by using “caches,” small, local memory banks that store frequently used data and cut down on time- and energy-consuming communication with off-chip memory.

Today’s chips generally have three or even four different levels of cache, each of which is more capacious but slower than the last. The sizes of the caches represent a compromise between the needs of different kinds of programs, but it’s rare that they’re exactly suited to any one program.

We've designed a system that reallocates cache access on the fly, to create new “cache hierarchies” tailored to the needs of particular programs.

We tested the system on a simulation of a chip with 36 cores, or processing units. We found that, compared to its best-performing predecessors, the system increased processing speed by 20 to 30 percent while reducing energy consumption by 30 to 85 percent.

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