Joel Emer is a Professor of the Practice in the Computer Science and Electrical Engineering department at MIT. He also spends part time as a Senior Distinguished Research Scientist at Nvidia in Westford, MA, where he is responsible for exploration of future architectures as well as modeling and analysis methodologies. Prior to joining NVIDIA, he worked at Intel where he was an Intel Fellow and Director of Microarchitecture Research. Previously he worked at Compaq and Digital Equipment Corporation.
He has held various research and advanced development positions investigating processor micro-architecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation. He has also been recognized for his contributions in the advancement of simultaneous multi-threading technology, analysis of the architectural impact of soft errors, memory dependence prediction, pipeline and cache organization, performance modeling methodologies and spatial architectures. His current research interests include memory hierarchy design, processor reliability, spatial architectures and performance modeling.
He received a bachelor's degree with highest honors in electrical engineering in 1974, and his master's degree in 1975 -- both from Purdue University. He earned a doctorate in electrical engineering from the University of Illinois in 1979. Emer holds over 25 patents and has published more than 40 papers. He is a Fellow of both the ACM and the IEEE and a member of the NAE, and was the 2009 recipient of the Eckert-Mauchly award for lifetime contributions in computer architecture.