Reducing Errors in Quantum Computation via Program Transformation

Abstract: Quantum computing promises exponential speedups for an important class of
problems. While quantum computers with few tens of qubits have already been demonstrated and
machines with 100+ qubits are expected soon, these machines face significant reliability
challenges – including gate error rates in the range of 1-2%, and measurement error rates in the
range of 5-10%. As these machines do not have sufficient capacity to do error correction (which
can incur 20x-50x physical qubits to form one fault-tolerant qubit), these machines are operated
in the Noisy Intermediate Scale Quantum (NISQ) mode of computing. The computation on a
NISQ machine can produce incorrect output. Therefore, the NISQ program is run thousands of
times and the output log is analyzed to infer the correct output. However, the error rates are such
that the likelihood of obtaining the right answer is still quite small for NISQ machines and this
problem only becomes worse for programs with a large number of instructions.
In this talk, I will discuss some of our recent work that aims to improve the reliability of near
term quantum computers by developing software techniques to mitigate the hardware errors. Our
first work (ASPLOS 2019) exploits the variability in the error rates of qubits to steer more
operations towards qubits with lower error rates and avoid qubits that are error-prone. Our
second work (MICRO 2019) looks at executing different versions of the programs tuned to cause
diverse mistakes so that the machine is less vulnerable to correlated errors, thereby making it
easier to infer the correct answer. Our third work (MICRO 2019) looks at exploiting the statedependent
bias in measurement errors (state 1 is more error prone than state 0) and dynamically
flips the state of the qubit to perform the measurement in the stronger state. We perform our
evaluations on real quantum machines from IBM and demonstrate significant improvement in the
overall system reliability. If time permits, I will also briefly discuss the hardware aspect of
designing quantum computers, including cryogenic processor and cryogenic memory system.
Brief Bio: Moinuddin Qureshi is a Professor of Electrical and Computer Engineering at the Georgia
Institute of Technology. His research interests include computer architecture, memory systems,
hardware security, and quantum computing. Previously, he was a research staff member (2007-
2011) at IBM T.J. Watson Research Center, where he developed the caching algorithms for Power-7
processors. He is a member of the Hall of Fame for ISCA, MICRO, and HPCA. His research has been
recognized with the best paper award at MICRO 2018, best paper award at Computing Frontiers
2019, best paper award at HiPC 2014, and two selections (and three honorable mentions) at IEEE
MICRO Top Picks. His ISCA 2009 paper on Phase Change Memory was recently awarded the 2019
Persistent Impact Prize in recognition of “exceptional impact on the fields of study related to nonvolatile
memories”. He was the Program Chair of MICRO 2015 and Selection Committee Co-Chair of
Top Picks 2017. He received his Ph.D. (2007) and M.S. (2003) from the University of Texas at Austin.
**Refreshments at 2:45