A Hardware Accelerator for Tracing Garbage Collection
Host
Malte Schwarzkopf
Parallel and Distributed Operating Systems group, CSAIL
Location: G882 (Hewlett Room)
*** Note changed time -- now 10:00am! ***
Abstract:
A large number of workloads are written in garbage-collected languages and these applications spend up to 10-35% of their CPU cycles and energy on GC. As this amounts to a significant fraction of cycles in scenarios ranging from data centers to mobile devices, reducing the cost of GC would improve the efficiency of a wide range of workloads.
In this talk, I will show how to reduce these overheads by moving garbage collection into a small hardware accelerator that is located close to the memory controller and performs GC more efficiently than a CPU. I will first present a general design of such a GC accelerator and describe how it can be integrated into both stop-the-world and pause-free collectors. I will then describe an end-to-end RTL prototype of this design, integrated into a RISC-V System-on-Chip (SoC) executing full Java benchmarks running on top of Linux on FPGAs.
This work was done at UC Berkeley.
Speaker bio:
Martin Maas is a Research Scientist in the Google Brain team. His research interests are in language runtimes, computer architecture and systems. His current work focuses on applying machine learning to systems problems. Before joining Google, Martin completed his PhD at UC Berkeley working with Krste Asanovic and John Kubiatowicz.
*** Note changed time -- now 10:00am! ***
Abstract:
A large number of workloads are written in garbage-collected languages and these applications spend up to 10-35% of their CPU cycles and energy on GC. As this amounts to a significant fraction of cycles in scenarios ranging from data centers to mobile devices, reducing the cost of GC would improve the efficiency of a wide range of workloads.
In this talk, I will show how to reduce these overheads by moving garbage collection into a small hardware accelerator that is located close to the memory controller and performs GC more efficiently than a CPU. I will first present a general design of such a GC accelerator and describe how it can be integrated into both stop-the-world and pause-free collectors. I will then describe an end-to-end RTL prototype of this design, integrated into a RISC-V System-on-Chip (SoC) executing full Java benchmarks running on top of Linux on FPGAs.
This work was done at UC Berkeley.
Speaker bio:
Martin Maas is a Research Scientist in the Google Brain team. His research interests are in language runtimes, computer architecture and systems. His current work focuses on applying machine learning to systems problems. Before joining Google, Martin completed his PhD at UC Berkeley working with Krste Asanovic and John Kubiatowicz.