Unblocking CPU Performance Bottlenecks for Data Center Workloads

Abstract:
Modern complex data center applications exhibit unique characteristics
such as extensive data and instruction footprints, complex control
flow, and hard-to-predict branches that are not adequately served by
existing microprocessor architectures. In particular, these workloads
exceed the capabilities of microprocessor structures such as the
instruction cache, BTB, branch predictor, and data caches, causing
significant degradation of performance and energy efficiency.
In my talk, I will provide a characterization of data center
applications, highlighting the importance of addressing frontend and
backend performance issues. I will then introduce new techniques to
address these challenges by improving the branch predictor, data
cache, and instruction scheduler. I will make the case for
profile-guided optimizations that amortize overheads across the fleet,
which have been successfully deployed at Google and Intel, serving
millions of users daily.

Bio:
Heiner Litz is an Associate Professor at UC Santa Cruz, a visiting
Professor at MIT, and a consulting CPU architect at ARM. His research
focuses on improving the performance, cost, and efficiency of data
center systems. Heiner is the recipient of the NSF CAREER award,
Intel's Outstanding Researcher award, a MICRO Best Paper award, two
IEEE MICRO Top Pick awards, and multiple Google Faculty Awards. Before
joining UCSC, Heiner Litz was a researcher at Google and a
postdoctoral research fellow at Stanford University with Prof.
Christos Kozyrakis and David Cheriton. He received his Diplom and
Ph.D. from the University of Mannheim, Germany, advised by Prof.
Bruening.

Headshot:
https://people.ucsc.edu/~hlitz/hlitz.jpeg

web:
https://people.ucsc.edu/~hlitz/