Research

Impact Areas

Lead

Saman Amarasinghe

Research Group

Computation Structures Group

Our mission is fostering the creation and development of high-performance, reliable and secure computing systems that are easy to interact with.

+21

Leads

Srini Devadas

Daniel Sanchez

Armando Solar-Lezama

Arvind

Research Areas

Impact Areas

Lead

Srini Devadas

Daniel Sanchez

Armando Solar-Lezama

Arvind

Research Group

Supertech Research Group

We investigate the technologies that support scalable high-performance computing, including hardware, software, and theory.

Charles E. Leiserson

Neil Thompson

Leads

Charles E. Leiserson

Neil Thompson

Research Areas

Algorithms & Theory

Impact Areas

Lead

Charles E. Leiserson

Neil Thompson

Charles E. Leiserson

Neil Thompson

Community of Research

Systems Community of Research

The Systems CoR is focused on building and investigating large-scale software systems that power modern computers, phones, data centers, and networks, including operating systems, the Internet, wireless networks, databases, and other software infrastructure.

+21

Sam Madden

Leads

Sam Madden

Research Areas

Impact Areas

Lead

Sam Madden

Sam Madden

17 Project Results matching all criteria

Project

Kami: A Modular Deductive Hardware Verification Platform

A framework to support implementing, specifying, verifying, and compiling hardware designs, modularly

Adam Chlipala

Leads

Adam Chlipala

Research Areas

Impact Areas

Adam Chlipala

Project

Weak Memory Models

Design and evaluation of novel weak memory models for multicores

Leads

Research Areas

Project

Pervasive Parallelism with the Swarm Architecture

Our research aims to scale hard-to-parallelize applications through new programming models and multicore architectures. Our goal is to enable
programmers to write efficient and scalable parallel programs as easily as they
write sequential programs today.

Daniel Sanchez

Victor Ying

Leads

Daniel Sanchez

Victor Ying

Research Areas

Daniel Sanchez

Victor Ying

Project

BlueDBM: Distributed Flash Storage for Big Data Analytics

BlueDBM is an architecture of computer clusters consisting of fast distributed flash storage and in-storage accelerators, which often outperforms larger and more expensive clusters in applications such as graph analytics.

Leads

Research Areas

Impact Areas

Project

Tardis: Cache Coherence for 1000-core Processors

Tardis is a new cache coherence protocol that performs and scales better than traditional coherence protocols and is simpler to implement

Leads

Research Areas

Project

Tiramisu Compiler

Commit Group

A polyhedral compiler for expressing image processing, DNN, and linear/tensor algebra applications

Saman Amarasinghe

Leads

Saman Amarasinghe

Research Areas

Impact Areas

Saman Amarasinghe

Project

Using Bitcoin to prevent identify theft

System piggybacks on the digital currency’s security protocols to thwart hijacked servers.

Srini Devadas

Leads

Srini Devadas

Research Areas

Impact Areas

Srini Devadas

Project

Jenga: Using chip memory more efficiently

Our system for generating ad hoc “cache hierarchies” increases processing speed while reducing energy consumption

Leads

Research Areas

Impact Areas

Energy

Project

Secure Demand Paging for Trusted Execution Environments

This project focuses on altering the way trusted execution environments handle paging to decouple page access patterns from the control flow of the program, preventing an attacker from using these access patterns to learn information about program secrets.

Srini Devadas

Leads

Srini Devadas

Research Areas

Srini Devadas

Project

Sanctum Secure Processor

An open-source, minimal secure processor

Victor Costan

Leads

Research Areas

Victor Costan

Project

[Inactive] T-1000: A Thousand-Core Coherent Shared Memory System

(This project is no longer active.) The T-1000, a prototype system of a thousand realistic processors embedded throughout an ensemble of interconnected FPGAs, seeks to demonstrate the scalability of timestamp-based cache coherence protocols on distributed shared memory systems.

Quan Nguyen

Leads

Quan Nguyen

Research Areas

Spoken Language Systems Group

Quan Nguyen

Project

Low-Power Speech Processing Circuits

The creation of low-power circuits capable of speech recognition and speaker verification will enable spoken interaction on a wide variety of devices in the era of Internet of Things.

Leads

Research Areas

Impact Areas

Project

KPart: A novel technique for partitioning shared caches

KPart is a cache partitioning-sharing technique that unlocks significant performance on current commodity multicore systems.

Leads

Research Areas

Project

Hemiola: Structural Design and Proof of Cache-Coherence Protocols

A Coq framework for structural design and proof of hierarchical cache-coherence protocols

Adam Chlipala

Leads

Adam Chlipala

Research Areas

Adam Chlipala

Project

Tapir

Supertech Research Group

Tapir is a compiler intermediate representation that aims to empower compilers to optimize parallel programs on multicore machines.

Leads

Charles E. Leiserson

William Moses

Tao Schardl

Research Areas

Project

Artificial Social Intelligence for Successful Teams (ASIST)

Computational Cognitive Science Group

Model-Based Embedded and Robotics Systems Group

Our goal is to develop a socially intelligent team coacher agent that helps humans communicate, strategize, and work together efficiently.

Leads

Howard Shrobe

Brian Williams

Boris Katz

Zhutian Yang

Research Areas

Robotics

Impact Areas

Health Care

Transportation

Project

Starling: Query Optimization for Cloud Services

Data Systems Group

Starling is a scalable query execution engine built on cloud function services that computes at a fine granularity, helping people more easily match workload demand.

Sam Madden

Matthew Perron

Leads

Sam Madden

Matthew Perron

Research Areas

Algorithms & Theory

Impact Areas

Simit: A Language for Computing on Sparse Systems

Sam Madden

Matthew Perron

10 People Results matching all criteria

PI
Core/Dual

Saman Amarasinghe

Professor

Compilers, architectures, software engineering

E saman@csail.mit.edu

T 253-8879

Lead

Commit Group

Tiramisu Compiler

Member

Taco: The Tensor Algebra Compiler

Halide

OpenTuner: An Extensible Framework for Program Autotuning

Program Performance Prediction with Deep Learning

Decentralized Information Group

Compilers, architectures, software engineering

PI
Core/Dual

Tim Berners-Lee

Professor

Systems, privacy, inventor of the World Wide Web

E timbl@w3.org

T 253-5702

Lead

World Wide Web Consortium

Solid: Social Linked Data

Member

Kami: A Modular Deductive Hardware Verification Platform

Systems, privacy, inventor of the World Wide Web

PI
Core/Dual

Adam Chlipala

Associate Professor

Programming languages, formal methods, security & privacy, systems

E adamc@csail.mit.edu

T 324-8439

Lead

Compilation Using Correct-by-Construction Program Synthesis

Hemiola: Structural Design and Proof of Cache-Coherence Protocols

Member

Compilation Using Correct-by-Construction Program Synthesis

Programming with spaces

FSCQ: File-system verification

Programming languages, formal methods, security & privacy, systems

PI
Core/Dual

Srini Devadas

Professor

Architectures, security, computer-aided design

E devadas@csail.mit.edu

T 253-0454

Lead

Using Bitcoin to prevent identify theft

Secure Demand Paging for Trusted Execution Environments

Scaling strong anonymity

Return of the Byzantine Generals

Member

Sanctum Secure Processor

A new way of handling all-to-all broadcast

Architectures, security, computer-aided design

PI
Core/Dual

Joel Emer

Professor of the Practice

Architectures, performance modeling

E emer@csail.mit.edu

T 258-9190

Member

Pervasive Parallelism with the Swarm Architecture

Architectures, performance modeling

PI
Core/Dual

Daniel Sanchez

Associate Professor

Architectures, systems, parallel computing, multicores, memory

E sanchez@csail.mit.edu

T 715-4886

Lead

Pervasive Parallelism with the Swarm Architecture

Member

Jenga: Using chip memory more efficiently

KPart: A novel technique for partitioning shared caches

Risk-aware Network Resource Allocation

Architectures, systems, parallel computing, multicores, memory

PI
Core/Dual

Howard Shrobe

Principal Research Scientist

Architectures, cybersecurity, web policy

E hes@csail.mit.edu

T 253-7877

Lead

RADMAX

Automated Attack Tree Generation for Critical Infrastructure

Securing IoT

Cognitive AI Community of Research

Artificial Social Intelligence for Successful Teams (ASIST)

Uhura: Personal Assistant that Manages Risk

Member

Internet Policy Research Initiative

Architectures, cybersecurity, web policy

PI
Core/Dual

Gerald Sussman

Professor

Artificial intelligence, supercomputers

E gjs@csail.mit.edu

T 253-5874

RM 32/ 32-G508/ G514

Lead

Sussman Lab

The Car Can Explain!

Member

Cognitive AI Community of Research

Internet Policy Research Initiative

Artificial intelligence, supercomputers

PI
Core/Dual

Daniel Weitzner

Principal Research Scientist

Web policy, cybersecurity, web architecture

E djweitzner@csail.mit.edu

T 253-8036

Lead

Keys Under Doormats

Parallel and Distributed Operating Systems

Member

Data Systems Group

Web policy, cybersecurity, web architecture

PI
Core/Dual

Nickolai Zeldovich

Associate Professor

Operating systems, hardware, programming languages

E nickolai@csail.mit.edu

T 253-6005

Lead

Scaling Filesystems To Many Cores

Vuvuzela: Metadata private messaging

Perennial

Member

FSCQ: File-system verification

Operating systems, hardware, programming languages

8 News Results matching all criteria

Algorithms & Theory AI & ML Computational Biology Computer Architecture Graphics & Vision Human-Computer Interaction Programming Languages & Software Engineering Robotics Security & Cryptography Systems & Networking Cybersecurity Education Energy Entertainment Health Care Manufacturing Transportation Wireless

June 27 '19

CSAIL hosts first-ever TEDxMIT

Speakers — all women — discuss everything from gravitational waves to robot nurses

CSAIL hosts first-ever TEDxMIT

Algorithms & Theory Computer Architecture Big Data Cybersecurity Health Care Internet of Things Manufacturing

January 31 '19

MIT hosts workshop on theoretical foundations of deep learning

Last week MIT’s Institute for Foundations of Data Science (MIFODS) held an interdisciplinary workshop aimed at tackling the underlying theory behind deep learning. Led by MIT professor Aleksander Madry, the event focused on a number of research discussions at the intersection of math, statistics, and theoretical computer science.

MIT hosts workshop on theoretical foundations of deep learning

Thomas Bourgeat, Andrew Wright, Arvind and Sizhou Zhang

Computer Architecture Security & Cryptography Cybersecurity Energy

October 22 '18

Opening up open-source to design better chips

MIT CSAIL system lets users change one part of a processor’s design without impacting the others

Opening up open-source to design better chips

Tim Berners-Lee was honored with the Turing Award for his work inventing the World Wide Web, the first web browser, and "the fundamental protocols and algorithms [that allowed] the web to scale."

Computer Architecture Big Data Cybersecurity Education Energy Entertainment Health Care Internet of Things Wireless

May 02 '18

From Utopia to Dystopia in 29 Short Years

May 2, 2018 - Sir Tim Berners-Lee of MIT gave a Dertouzos Distinguished Lecture titled "From Utopia to Dystopia in 29 Short Years."

From Utopia to Dystopia in 29 Short Years

Computer Architecture Security & Cryptography Cybersecurity

February 01 '18

MIT security experts discuss “Spectre” and “Meltdown” processor flaws

Last week CSAIL hosted the second “Hot Topics in Computing” speaker series, a monthly forum where computing experts hold discussions with community members on various topics in the computer science field.

MIT security experts discuss “Spectre” and “Meltdown” processor flaws

Computer Architecture Programming Languages & Software Engineering Big Data

October 30 '17

Faster big-data analysis

We live in the age of big data, but most of that data is “sparse.” Imagine, for instance, a massive table that mapped all of Amazon’s customers against all of its products, with a “1” for each product a given customer bought and a “0” otherwise. The table would be mostly zeroes.

Faster big-data analysis

Computer Architecture Security & Cryptography Cybersecurity

October 22 '17

Selective memory

In a traditional computer, a microprocessor is mounted on a “package,” a small circuit board with a grid of electrical leads on its bottom. The package snaps into the computer’s motherboard, and data travels between the processor and the computer’s main memory bank through the leads.

Selective memory

Researchers from CSAIL have devised a new system for data center caching that uses flash memory. In addition to costing less and consuming less power, a flash caching system could dramatically reduce the number of cache servers required by a data center.

Computer Architecture Big Data

September 04 '17

Making data centers more energy efficient

Most modern websites store data in databases, and since database queries are relatively slow, most sites also maintain so-called cache servers, which list the results of common queries for faster access. A data center for a major web service such as Google or Facebook might have as many as 1,000 servers dedicated just to caching.

Making data centers more energy efficient

4 Group Results

Research Group

Commit Group

Saman Amarasinghe

Leads

Saman Amarasinghe

Research Areas

Impact Areas

Lead

Saman Amarasinghe

Research Group

Computation Structures Group

Our mission is fostering the creation and development of high-performance, reliable and secure computing systems that are easy to interact with.

+21

Leads

Srini Devadas

Daniel Sanchez

Armando Solar-Lezama

Arvind

Research Areas

Impact Areas

Lead

Srini Devadas

Daniel Sanchez

Armando Solar-Lezama

Arvind

Research Group

Supertech Research Group

We investigate the technologies that support scalable high-performance computing, including hardware, software, and theory.

Charles E. Leiserson

Neil Thompson

Leads

Charles E. Leiserson

Neil Thompson

Research Areas

Algorithms & Theory

Impact Areas

Lead

Charles E. Leiserson

Neil Thompson

Charles E. Leiserson

Neil Thompson

Community of Research

Systems Community of Research

+21

Sam Madden

Leads

Sam Madden

Research Areas

Impact Areas

Lead

Sam Madden

Sam Madden

17 Project Results

Project

[Inactive] T-1000: A Thousand-Core Coherent Shared Memory System

Quan Nguyen

Leads

Quan Nguyen

Research Areas

Quan Nguyen

Project

Artificial Social Intelligence for Successful Teams (ASIST)

Computational Cognitive Science Group

Model-Based Embedded and Robotics Systems Group

Our goal is to develop a socially intelligent team coacher agent that helps humans communicate, strategize, and work together efficiently.

Leads

Howard Shrobe

Brian Williams

Boris Katz

Zhutian Yang

Research Areas

Robotics

Impact Areas

Health Care

Transportation

Project

BlueDBM: Distributed Flash Storage for Big Data Analytics

Leads

Research Areas

Impact Areas

Project

Hemiola: Structural Design and Proof of Cache-Coherence Protocols

A Coq framework for structural design and proof of hierarchical cache-coherence protocols

Adam Chlipala

Leads

Adam Chlipala

Research Areas

Adam Chlipala

Project

Jenga: Using chip memory more efficiently

Our system for generating ad hoc “cache hierarchies” increases processing speed while reducing energy consumption

Leads

Research Areas

Impact Areas

Energy

Project

Kami: A Modular Deductive Hardware Verification Platform

A framework to support implementing, specifying, verifying, and compiling hardware designs, modularly

Adam Chlipala

Leads

Adam Chlipala

Research Areas

Impact Areas

Adam Chlipala

Project

KPart: A novel technique for partitioning shared caches

KPart is a cache partitioning-sharing technique that unlocks significant performance on current commodity multicore systems.

Leads

Research Areas

Spoken Language Systems Group

Project

Low-Power Speech Processing Circuits

The creation of low-power circuits capable of speech recognition and speaker verification will enable spoken interaction on a wide variety of devices in the era of Internet of Things.

Leads

Research Areas

Impact Areas

Project

Pervasive Parallelism with the Swarm Architecture

Daniel Sanchez

Victor Ying

Leads

Daniel Sanchez

Victor Ying

Research Areas

Daniel Sanchez

Victor Ying

Project

Sanctum Secure Processor

An open-source, minimal secure processor

Victor Costan

Leads

Research Areas

Victor Costan

Project

Secure Demand Paging for Trusted Execution Environments

Srini Devadas

Leads

Srini Devadas

Research Areas