Accelerating Multiprocessor Simulation with a Memory Timestamp Record
Speaker: Kenneth C. Barr ,
Date: March 7 2005
Time: 4:05PM to 5:00PM
Location: Star seminar room (32-D463)
Contact: Louis-Philippe Morency, 617-253-4278, lmorency@csail.mit.edu
Relevant URL: http://cag.csail.mit.edu/scale/papers/mtr-ispass05.pdf
Computer architects rely heavily on software simulators to evaluate, refine, and validate new designs before implementation, but modern multiprocessors have a growing amount of microarchitectural state which must be "warmed" before detailed simulation to avoid cold-start effects. Some industry development groups report detailed warming requires up to two weeks when starting from stored architectural checkpoints.
To address this bottleneck, we introduce a fast and accurate technique for warming the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestamp record (MTR). The MTR is a versatile, compressed snapshot of memory reference patterns which can be rapidly updated during fast-forwarded simulation, or stored as part of a checkpoint.
In this talk, I will describe the structure, features, and operation of the MTR. In addition, I describe our full-system simulation framework, which models a directory-based cache-coherent multiprocessor running a range of multithreaded workloads. With this framework, we find the MTR's performance predictions to be within 15% of our detailed model while running up to 7.7X faster.
Joint work with: Heidi Pan, Michael Zhang, and Krste Asanovic
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