Beehive, a multi-core platform for low-level systems research
Speaker: Andrew Birrell , Microsoft ResearchContact:
Date: November 11 2009
Time: 3:30PM to 4:30PM
Location: 8th floor reading room
Host: Frans Kaashoek, MIT
Frans Kaashoek, email@example.comRelevant URL:
At MSR Silicon Valley we have been developing a new multi-core processor, implemented by configuring an FPGA. On an entry-level Xilinx FPGA (like the evaluation board sold to universities for $750), we have today a 13-core 100 MHz RISC computer that occupies about half of the FPGA. This includes memory system and Ethernet controller. We currently have a compilation environment for C, and we hope to be able to support MSIL (C# and its friends).
The goal of the project is to enable systems research of the sort that starts from the bare metal (no operating systems getting in the way), and that explores questions at the boundary of “systems software” and “computer architecture”. In particular, it’s perfectly reasonable for a suitably skilled researcher to change the computer’s architecture to suit, with turnaround times measured in hours, or perhaps days, but not months or years. This will permit exploration of questions about future designs without the limitations imposed by simulators, and with much greater credibility than simulation results.
For example, the platform would be ideal for an apples-to-apples comparison of transactional memory versus more traditional synchronization. Or for an evaluation of the trade-offs between coherent shared memory and message passing systems. We expect to be able to give the research platform to universities for free in due course (boards not included).
This is work-in-progress. I’ll explain what we have, how it works, and what we’re still working on.
See other events that are part of
See other events happening in November 2009