CSAIL Event Calendar: Previous Series

Preventing Memory Performance Attacks in Multi-core Systems

Speaker: Onur Mutlu , Microsoft Research and University of Texas at Austin
Date: April 23 2008
Time: 4:00PM to 5:00PM
Location: Patil/Kiva Conference Room, 32-G449
Host: Arvind, MIT - CSAIL

Current multi-core processors are vulnerable to a new class of Denial of Service attacks because of their shared memory systems. A low-importance application can intentionally or unintentionally destroy the performance of a high-importance one running on the same chip. We call such an aggressive application a memory performance hog (MPH). With the widespread deployment of multi-core systems in commodity computers and with the rapid increase in the number of on-chip cores, we expect MPHs to become a prevalent security and performance issue that could affect almost all computer users.

I will describe our solution to the problem, "stall-time fair memory scheduling (STFM)," that provides performance-fairness to threads sharing the memory system. STFM's goal is to equalize the memory-related slowdown experienced by equal-priority threads due to interference from other threads, while also improving overall system performance. STFM not only effectively contains memory performance hogs and provides fair memory access but also improves system utilization. I will describe how STFM is seamlessly exposed to the system software to provide different levels of memory service to threads with different priorities/weights and to enable the enforcement of different software-based Quality-of-Service policies. Our evaluations show that STFM provides a flexible, low-cost, and high-performance fairness substrate for multi-core memory systems.

Bio:

Onur Mutlu is a researcher at Microsoft Research. He is broadly interested in computer architecture and systems research, especially in making computers more robust (controllable, reliable, and secure) and faster through hardware/software cooperation. He received his PhD and MS in Electrical and Computer Engineering from UT-Austin in 2006 and his BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. During his graduate studies, he worked at Intel Corporation for three summers and at Advanced Micro Devices for two summers, participating in the design of next-generation microprocesssors. He was a recipient of the Intel PhD fellowship in 2004 and the University of Texas George H. Mitchell Award for Excellence in Graduate Research in 2005 for his dissertation research on "efficient runahead execution processors."

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