A Vertically Integrated Architecture Design Approach to Address Technology Scaling Trends
Speaker: Karu Sankaralingam , University of Wisconsin-Madison
Date: February 28 2008
Time: 4:00PM to 5:00PM
Location: 32-G449
Host: Arvind, MIT
Contact: Francis Doughty, 3-4602, doughty@mit.edu
Relevant URL: Abstract:
Technology constraints have fundamentally driven the evolution of
microprocessors. Wire delays, power, and microarchitectural pipelining
limits have triggered a shift to multi-core processors. In the initial
part of this talk, I will briefly summarize the TRIPS project in which
we took a different approach to concurrency driven by these technology
trends. I will highlight two aspects: 1) the key principle of
expressing dependences efficiently to the hardware and 2) my extensive
system building experience in the TRIPS project.
I will then describe my ongoing research which has a long term
technology-driven vision. Scaling to the end of silicon technology and
the transition to post-CMOS devices is introducing an era of non-ideal
process scaling. First, transistors are becoming increasingly
unreliable. Second, the power efficiency of an individual transistor
is only slowly growing every generation and lags the device
integration growth. However, conventional microprocessor designs hide
this device behavior and attempt to maintain an illusion of perfection
at all levels of the system stack: an illusion that is becoming
prohibitively expensive to maintain. Applications are also changing,
and emerging new classes of applications are increasingly relying on
probabilistic methods and have an inherent tolerance for
uncertainty. This provides an opportunity to creatively utilize
hardware.
I will make the case that a vertically integrated approach that
exposes device properties through layers of the system stack and an
understanding of application behavior is essential for efficient
architectures as technology scales. Specifically, concurrency and
error tolerance are first order primitives that architectures must
handle. To motivate this vision, I will describe our ongoing work in
bridging technology scaling trends all the way up to the application
layer. I will characterize emerging applications and outline
architectural and microarchitectural mechanisms to exploit their
probabilistic behavior. I will then, describe one specific instance of
this integrated approach: our real-time ray tracing system where we
are simultaneously examining graphics algorithms, simulations and
analytical models, architecture, and technology trends to build a
programmable real-time ray tracing system. Our results show promise
for a variety of emerging applications and many opportunities for
innovation across system boundaries.
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